Physical Design Methodology Engineer, AI HW IP
About this role
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
Our IP delivery timelines are set as much by flow maturity as by design work. This role develops, deploys, and owns the RTL-to-GDSII methodology the IP physical design team runs on, so a new block, node, or customer variant starts from a working flow instead of a cold start.
This role is hybrid, based out of Toronto, ON; Austin, TX, or Belgrade, Serbia.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
- A physical design or CAD methodology engineer who has built flows that production teams depend on daily.
- Automation-minded, happiest when you are removing manual steps and making PPA exploration repeatable.
- Building with AI as part of how you develop flows, and opinionated about where LLMs and ML-driven optimization genuinely help versus where they do not.
- An effective partner to design teams and EDA vendors, and a clear writer who documents flows well enough that others can run them without you.
What We Need
- An Engineer with 5+ years developing and supporting physical design methodology or CAD flows in production use.
- Expertise with industry-standard tools (FusionCompiler/ICC2, Innovus/Genus, PrimeTime, RedHawk) and scripting languages (Tcl, Python, Perl).
- Deep understanding of advanced node methodology, low-power intent (UPF/CPF), clock tree synthesis, and signoff (EM/IR, DRC/LVS).
- Experience standing up flows for new technology nodes, PDKs, or foundry targets ahead of program need, and qualifying new EDA releases.
What You Will Learn
- How to build and scale EDA automation for AI accelerators and high-performance CPUs on advanced FinFET/GAA nodes.
- ML-driven flow optimization and custom CAD development at production scale.
- How to influence EDA vendor roadmaps through direct technical partnership.
- How multi-variant, multi-foundry IP delivery works, and how flow readiness moves customer commit dates.
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
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