Principal Design Verification Engineer
sambanovasystems
Principal Design Verification Engineer
asteralabs· Design Verification CCE2
About this role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
We are seeking talented Design Verification Professionals with proven expertise in industry-standard protocols such as PCIe and CXL. You will play a key role in the functional verification of designs, from developing block-level and system-level verification plans to writing test sequences, executing tests, and collecting and closing coverage.
Responsibilities:
- Develop and execute block-level and system-level verification plans.
- Write and execute test sequences and collect and close coverage.
- Collaborate with RTL designers to debug failures and refine verification processes.
- Utilize coding and protocol expertise to contribute to functional verification.
- Develop user-controlled random constraints in transaction-based verification methodologies.
- Write assertions, cover properties, and analyze coverage data.
- Create VIP abstraction layers for sequences to simplify and scale verification deployments.
Basic Qualifications:
- Minimum of 12 years’ experience in supporting or developing complex SoC/silicon products for server, storage, and/or networking applications.
- Strong academic and technical background in Electrical Engineering or Computer Engineering (bachelor’s degree required, master’s preferred).
- Professional attitude with the ability to prioritize tasks, prepare for customer meetings, and work independently with minimal guidance.
- Knowledge of industry-standard simulators, revision control systems, and regression systems.
- Entrepreneurial, open-minded behavior and a can-do attitude, with a focus on customer satisfaction.
Required Experience:
- Interpreting PCIe/CXL standard protocol specifications to develop and execute verification plans in simulation environments.
- Experience using Verification IPs from third-party vendors for PCIe/CXL, focusing on Gen3 or above.
- Ability to independently develop test plans and sequences in UVM to generate stimuli.
- Experience writing assertions, cover properties, and analyzing coverage data.
- Developing VIP abstraction layers for sequences to simplify and scale verification deployments.
Preferred Experience:
- Expertise in verifying Physical Layer, Link Layer, and Transaction Layer of PCIe/CXL protocols, including compliance on PCIe/CXL EP/RC.
- Experience with buffering and queuing with QoS on complex NOC-based SoCs.
- Analyzing performance at the system level on switching fabrics.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Frequently Asked Questions
Is the salary disclosed for the Principal Design Verification Engineer position at asteralabs?
The salary for this Principal Design Verification Engineer role at asteralabs is not publicly listed. Click "Apply Now" to learn more about the compensation package on their official careers page.
Where is the Principal Design Verification Engineer position at asteralabs located?
This Principal Design Verification Engineer role at asteralabs is based in Bengaluru, Karnataka, India. The position is listed as on-site or hybrid. Check the full job description or apply directly to confirm the work arrangement.
Which team or department does the Principal Design Verification Engineer at asteralabs belong to?
This Principal Design Verification Engineer position is part of the Design Verification CCE2 department at asteralabs. See the full job description for more information about the team structure and responsibilities.
How do I apply for the Principal Design Verification Engineer position at asteralabs?
Click the "Apply Now" button on this page. You will be redirected to asteralabs's official application portal hosted on greenhouse where you can submit your application directly.
When was the Principal Design Verification Engineer job at asteralabs posted?
This Principal Design Verification Engineer position at asteralabs was posted on Aug 27, 2026. Apply as soon as possible — early applications are often reviewed first.
Principal Design Verification Engineer
asteralabs
You'll be redirected to asteralabs's official application page on Greenhouse.