Senior Design Verification Engineer
asteralabs
Tech Lead, Physical Design
asteralabs· Compute Connectivity Engineering 1
About this role
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Tech Lead Physical Design
Experience - 6-10 years
Bengaluru, India
Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.
Basic qualifications:
- Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE / Computer is required, and a Master’s degree is preferred.
- ≥6 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
- Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
- Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
Required experience:
- Hands-on and thorough knowledge of synthesis, place and route, CTS, extraction timing analysis/STA, Physical Verification and other backend tools and methodologies for technologies 16nm or less, preferably 7nm or less.
- Proven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level.
- Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production.
- Experience with Cadence and/or Synopsys physical design tools/flows.
- Familiarity and working knowledge of System Verilog/Verilog.
- Experience with DFT tools and techniques.
- Experience in working with IP vendors for both RTL and hard-mac blocks.
- Good scripting skills in python or Perl
Preferred :
- Good knowledge of design for test (DFT), stuck-at and transition scan test insertion.
- Familiarity with DFT test coverage and debug.
- Familiarity with ECO methodologies and tools.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Frequently Asked Questions
Is the salary disclosed for the Tech Lead, Physical Design position at asteralabs?
The salary for this Tech Lead, Physical Design role at asteralabs is not publicly listed. Click "Apply Now" to learn more about the compensation package on their official careers page.
Where is the Tech Lead, Physical Design position at asteralabs located?
This Tech Lead, Physical Design role at asteralabs is based in Bengaluru, Karnataka, India. The position is listed as on-site or hybrid. Check the full job description or apply directly to confirm the work arrangement.
Which team or department does the Tech Lead, Physical Design at asteralabs belong to?
This Tech Lead, Physical Design position is part of the Compute Connectivity Engineering 1 department at asteralabs. See the full job description for more information about the team structure and responsibilities.
How do I apply for the Tech Lead, Physical Design position at asteralabs?
Click the "Apply Now" button on this page. You will be redirected to asteralabs's official application portal hosted on greenhouse where you can submit your application directly.
When was the Tech Lead, Physical Design job at asteralabs posted?
This Tech Lead, Physical Design position at asteralabs was posted on Sep 11, 2026. Apply as soon as possible — early applications are often reviewed first.
Tech Lead, Physical Design
asteralabs
You'll be redirected to asteralabs's official application page on Greenhouse.